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LEON3

Wed, 21 Mar 2012 06:25:05 GMT

The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. The LEON3 processor has the following features: SPARC V8 instruction set with V8e extensionsAdvanced 7-stage pipeline Hardware multiply, divide and MAC units High-performance, fully pipelined IEEE-754 FPU Separate instruction and data cache (Harvard architecture) with snooping Configurable caches: 1 - 4 ways, 1 - 256 kbytes/way. Random, LRR or LRU replacement Local instruction and data scratch pad RAM, 1 - 512 Kbytes SPARC Reference MMU (SRMMU) with configurable TLBAMBA-2.0 AHB bus interfaceAdvanced on-chip...

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